The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Referring, now to FIG. 1A, a high level functional block diagram of synchronous logic is presented. One or more inputs are received by logic 100. The logic 100 may include combinational logic, such as an arrangement of logic gates. The logic 100 may have one or more outputs, one of which is shown being received by a flip-flop 104. Based on a received clock signal CK, the flip-flop 104 latches the value of the output from the logic 100. This latch value is then presented at an output of the flip-flop 104.
When the logic 100 has more than one output, flip-flops, including the flip-flop 104, may be used. In a pipelined system, one or more flip-flops may be present between each stage of the pipeline. In such an example. FIG. 1A may represent one stage of the pipeline, where the inputs to the logic 100 are received from flip-flops of the previous stage, and the output of the flip-flop 104 is provided to logic in the subsequent stage of the pipeline.
Referring now to FIG. 1B, a circuit diagram of a combinational logic is presented. For example, the components of FIG. 1B could be included in the logic 100 of FIG. 1A. A metal oxide semiconductor field-effect transistor (MOSFET) 110 includes a gate that receives input A1. A MOSFET 114 includes a gate that receives an input signal A2. The input signal A1 is also received by a gate of a MOSFET 118, while the input signal A2 is also received by a gate of a MOSFET 122.
Sources of the MOSFETs 118 and 122 are connected to a power supply VDD. The MOSFETs 110 and 114 are connected in series; a source of the MOSFET 114 is connected to a ground potential and a drain of the MOSFET 110 is connected to sources of the MOSFETs 118 and 122. The drain of the MOSFET 110 is provided as an output, labeled D. The output D is the logical NAND (NOT AND) of the inputs A1 and A2. The MOSFETs 110 and 114 are N-channel MOSFETs, while the MOSFETs 118 and 122 are P-channel MOSFETs.
Referring now to FIG. 2A, a functional schematic of a master-slave flip-flop is presented. For example only, the flip-flop of FIG. 2A may be used as the flip-flop 104 of FIG. 1A. FIGS. 2A and 2B are examples of flip-flops using principles of static logic. Logic signal D is received at first terminals of a MOSFET 140 and a MOSFET 144. Second terminals of the MOSFETs 140 and 144 are connected to an input of an inverter 148. An output of the inverter 148 is connected to an input of an inverter 152. An output of the inverter 152 is connected to the input of the inverter 148. A master portion 156 of the flip-flop includes the MOSFETs 140 and 144 and the inverters 148 and 152.
A slave portion 160 of the flip-flop receives an output of the inverter 148 at first terminals of MOSFETs 164 and 168. Second terminals of the MOSFETs 164 and 168 are connected to an input of an inverter 172. An output of the inverter 172 is connected to an input of an inverter 176. An output of the inverter 176 is connected to the input of the inverter 172. The output of the inverter 172 is output from the flip-flop and is, according to convention, labeled Q. A clock signal CK is received by gates of the MOSFETs 144 and 164. An inverter 180 provides an inverted version of the clock signal CK to gates of the MOSFETs 140 and 168.
The MOSFETs 140 and 164 are N-channel MOSFETs, while the MOSFETs 144 and 168 are P-channel MOSFETs. Together, the MOSFETs 140 and 144 form a pass gate, which is controlled by the clock signal CK. Similarly, the MOSFETs 164 and 168 also form a pass gate. When the clock signal CK is low, the input signal D is passed through the pass gate formed by the MOSFETs 140 and 144 and is buffered and inverted by the inverters 148 and 157.
When the clock signal transitions to high, the pass gate formed by the MOSFETs 164 and 168 connects the output of the master portion 156 to the inverters 172 and 176. At the same time, the pass gate formed by the MOSFETs 140 and 144 begins blocking the signal D so that changes to the signal D are not reflected at the output of the master portion 156. The output of the inverter 172, Q, therefore holds the value of D captured at the previous rising edge of the clock CK. When the clock signal CK falls, the pass gate formed by the MOSFETs 164 and 168 blocks signals from the output of the master portion 156, and the value of Q is therefore retained until the clock signal CK rises once again.
The inverters 148, 152, 172, and 176 may share a similar structure. For example only, the structure may include an N-channel MOSFET and a P-channel MOSFET in series, where the inverter input is connected to gates of the MOSFETs and where the inverter output is connected to the de between the MOSFETs.
Referring now to FIG. 2B, another implementation of a master slave flip-flop is shown. A clock signal CK and an inverted clock signal generated by an n 200 are received by gates of MOSFET 204 and MOSFET 208, respectively. An input D is received by first terminals of the MOSFETs 204 and 208, and second terminals of the MOSFETs 204 and 208 are connected to an inverter 212, which is connected in series with an inverter 216. An output of the inverter 216 is connected to the input of the inverter 212 via a pass gate formed by MOSFETs 220 and 224. Gates of the MOSFETs 220 and 224 receive the clock signal CK and the inverted clock signal, respectively.
The output of the inverter 216 is provided to an inverter 228 via a pass gate formed by MOSFETs 232 and 236. Gates of the MOSFETs 232 and 236 receive the clock signal CK and the inverted clock signal, respectively. The inverter 240 receives an output from the inverter 228 and outputs a signal to the input of the inverter 128 via a pass gate formed by MOSFETs 244 and 248. Gates of the MOSFETs 244 and 248 receive the inverted clock signal and the clock signal, respectively. The output of the inverter 240 is labeled Q. In comparison to FIG. 2A, FIG. 2B includes two additional pass gates. The pass gate formed by the MOSFETs 220 and 224 enables the inverters 212 and 216 to create a loop that retains the values of the input of the inverter 212 and the output of the inverter 216.
Referring now to FIG. 2C, a flip-flop using dynamic principles is presented. A clock signal CK is received by a gate of a MOSFET 280 and by an inverter 284. An output of the inverter 284 is received by an inverter 288, which provides an output to a NAND gate 292. The clock signal CK is also received by MOSFETs 296 and 300. Input signal D is received by MOSFET 304. A source of the MOSFET 296 is connected to a power supply VDD, and a source of the MOSFET 280 is connected to a ground potential. A MOSFET 308 is connected in series between the MOSFETs 296 and 304, while the MOSFET 304 is connected in series between the MOSFETs 308 and 280.
A gate of the MOSFET 308 receives an output of the NAND gate 292. The node between the MOSFETs 296 and 308 is connected to a second input of the NAND gate 292, an input of an inverter 312, and gates of MOSFETs 316 and 320. An output of the inverter 312 is provided to an input of an inverter 324. An output of the inverter 324 is tied back to the input of the inverter 312.
A source of the MOSFET 316 is connected to ground, while a source of the MOSFET 320 is connected to VDD. The MOSFET 300 is connected in series between the MOSFETs 320 and 316. The node between the MOSFETs 320 and 300 is connected to an input of an inverter 328. An output of the inverter 328 is connected to the input of the inverter 332, while an output of the inverter 332 is tied back to the input of the inverter 328. The output of the inverter 332 is labeled as the output Q, while the output of the inverter 328 is a logical complement of Q, labeled Q. While FIGS. 2A and 2B depict static logic, where input signals are simply latched by inverter feedback loops that are selectively connected to each other via pass gates, the dynamic logic FIG. 2C relies on evaluation of a dynamic node. The output of the inverter 324 and the input of the inverter 312 are connected to the dynamic node, and the voltage on the dynamic node is affected by the input signal D. By latching a result as the output Q based on the dynamic node, the value of the input signal is thereby determined and latched.
Referring now to FIG. 2D, another example of a flip-flop is presented. Input D is received by a gate of a MOSFET 350, while a logical complement of the input D is received by a gate of a MOSFET 354. A MOSFET 358 selectively connects sources of the MOSFETs 350 and 354 to a ground potential. Gates of the MOSFET 358 and MOSFETs 362 and 366 are controlled by a clock signal CK. The sources of the MOSFETs 362 and 366 are connected to VDD. A MOSFET 370 has a gate connected to VDD and is connected between drains of the MOSFETs 350 and 354.
Sources of MOSFETs 372 and 374 are connected to VDD. A MOSFET 378 is connected in series between the MOSFETs 372 and 350. A MOSFET 382 is connected in series between the MOSFETs 354 and 374. Gates of the MOSFETs 372 and 378 are connected to the node between the MOSFETs 374 and 382. Similarly, the gates of the MOSFETs 374 and 382 are connected to the node between the MOSFETs 372 and 378.
The node between the MOSFETs 372 and 378 is connected to the drain of the MOSFET 366 and to a first input of a NAND gate 386. The node between the MOSFETs 374 and 382 is connected to a drain of the MOSFET 362 and to a first input of a NAND gate 390. A second input of the NAND gate 386 is connected to an output of the NAND gate 390. Similarly a second input of the NAND gate 390 is connected to an output of the NAND gate 386.
As a result, the NAND gates 386 and 390 form a set-reset (SR) latch, and the first inputs to the NAND gates 386 and 390 are labeled S and R, respectively. The output of the NAND gate 386 is Q, while the output of the NAND gate 390 is the logical complement, labeled Q. In FIG. 2D, the flip-flop operates similarly to a differential amplifier having inputs of the input signal D and its logical complement. The outputs of the differential amplifier are labeled S and R, and are connected as set and reset signals, respectively, to an SR latch. The differential amplifier therefore controls the SR latch to output the appropriate signal Q in response to the input signal D.